We invite applications for a PhD position on the theme: High-Level Synthesis of Neural Networks for FPGAs with LIFT. This position is fully funded (for EU nationals) by a scholarship from Microsoft Research for 3.5 years which is the typical length of PhD studies. The starting date is flexible.

Machine-learning applications are becoming pervasive throughout our entire society. They are already used extensively in areas such as machine translation and business data analytic and are set to revolutionise our world with applications such as self-driving cars. This has become possible thanks to the massive amount of data available for training coupled with the development of powerful parallel hardware.

However, writing efficient parallel implementation for these algorithms remains a challenge for the non-experts. The presence of parallel accelerators such as GPUs (Graphic Processing Units) or FPGAs (Field-Programmable Gate Arrays) means that software has to be specifically written for these devices. Programmers have to use different programming models and often need to fine-tune their code for the special characteristics of the targeted hardware. This expensive and time-consuming process needs to be repeated every time new hardware emerge or even when the software stack is updated. To enable machine-learning expert to unlock the potential of future systems, we need to focus on new software programming model that abstract away most of the hardware details.

In this project, we propose to build upon our existing Lift project, an Open Source language and compiler initially developed at Edinburgh University. Lift combines a high-level functional data parallel language with a system of rewrite rules which encodes algorithmic and hardware-specific optimisation choices. An application written in Lift is able to take advantage of parallel accelerators available in the systems, transparently from the user. This proposal is about augmenting Lift with the ability to express and optimise machine-learning algorithms and exploit effectively FPGA hardware.

This is an opportunity to join and collaborate within a world-leading research group in computing systems coupled with an industrial connection. Applications from female candidates and minority groups are particularly welcome. This project will be supervised by Dr Christophe Dubach from the school of informatics at Edinburgh University.

Ideal candidates will have an excellent degree (BSc or MSc) in computer science or related discipline and a strong interest in compiler, architecture and programming languages for heterogeneous systems. The ideal candidate would have the following skills:

  • Hardware design experience (in VHDL or Verilog)
  • Good functional programming and object-oriented programming skills
  • Compiler knowledge
  • Basic understanding of machine-learning algorithms desirable

Candidates interested by this project should first contact Christophe by email (christophe.dubach@ed.ac.uk) attaching: a CV; transcripts (courses and grades achieved during BSc / MSc); and a short statement explaining how your background is relevant to this position.

Please apply by the 15th of April 2018 if you want your application to be fully considered. The ideal starting date would be around September 2018, but this is flexible.

This is a fully funded studentship for UK and EU students (tuition fees + living cost). We welcome non-EU applicants and can provide funding for EU fees and maintenance for such students. However, remaining fees will need to come from another source. We might be able to cover such fees for exceptional overseas candidates.